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Computer Organization Questions and Answers - Interrupts. This set of Computer Organisation and Architecture MCQ focuses on “Interrupts”. The interrupt- request line is a part of thea) Data lineb) Control linec) Address lined) None. View Answer Answer: b. Explanation: The Interrupt- request line is a control line along which the device is allowed to send the interrupt signal. The return address from the interrupt- service routine is stored on thea) System heapb) Processor registerc) Processor stackd) Memory. View Answer Answer: c. Explanation: The Processor after servicing the interrupts as to load the address of the previous process and this address is stored in the stack. The signal sent to the device from the processor to the device after recieving an interrupt isa) Interrupt- acknowledgeb) Return signalc) Service signald) Permission signal. View Answer Answer: a. Explanation: The Processor upon recieving the interrupt should let the device know that its request is received. When the process is returned after an interrupt service ______ should be loaded againi) Register contentsii) Condition codesiii) Stack contentsiv) Return addressesa) i,ivb) ii,iii and ivc) iii,ivd) i,ii. View Answer Answer: d.Explanation: None.The time between the recieval of an interrupt and its service is ______a) Interrupt delayb) Interrupt latencyc) Cycle timed) Switching time.View Answer Answer: b.Explanation: The delay in servicing of an interrupt happens due to the time taken for contect switch to take place.Interrupts form an important part of _____ systemsa) Batch processingb) Multitaskingc) Real- time processingd) Multi- user. Install Iphone Rom On Galaxy Y . View Answer Answer: c. Explanation: This forms an imporatant part of the Real time system since if a process arrives with greater priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced. A single Interrupt line can be used to service n different devicesa) Trueb) False. View Answer Answer: a. Explanation: None 8. XORiv) XNORa) i,iib) iic) ii,iiid) ii,iv. View Answer Answer: a. Explanation: None 9. The resistor which is attached to the service line is called _____a) Push- down resistorb) Pull- up resistorc) Break down resistord) Line resistor. View Answer Answer: b. Explanation: This resistor is used to pull up the voltage of the interrupt service line. An interrupt that can be temporarily ignored isa) Vectored interruptb) Non- maskable interruptc) Maskable interruptd) High priority interrupt. View Answer Answer: c. Explanation: The maskable interrupts are usually low priority interrupts which can be ignored if an higher priority process is being executed. The 8. 08. 5 microprocessor respond to the presence of an interrupta) As soon as the trap pin becomes ‘LOW’b) By checking the trap pin for ‘high’ status at the end of each instruction fetchc) By checking the trap pin for ‘high’ status at the end of execution of each instructiond) By checking the trap pin for ‘high’ status at regular intervals. View Answer Answer: c. Explanation: The 8. CPU as two modes privileged and non- privileged. In order to change the mode from privileged to non- privilegeda) A hardware interrupt is neededb) A software interrupt is neededc) Either a or bd) A non- privileged instruction (which does not generate an interrupt)is needed. View Answer Answer: b. Explanation: A software interrupt by some program which needs some c. PU service, at that time the two modes can be interchanged. Which interrupt is unmaskable…?? RST 5. 5b) RST 7. TRAPd) Both a and b. View Answer Answer: c. Explanation: The trap is a non- maskable interrupt as it deals with the on going process in the processor. THe trap is initiated by the process being executed due to lack of data required for its completion. Hence trap is unmaskable. From amongst the following given scenarios determine the right one to justify interrupt mode of data transferi) Bulk transfer of several kilo- byteii) Moderately large data transfer of more than 1kbiii) Short events like mouse actioniv) Keyboard inputsa) i and iib) iic) i,ii and ivd) iv. View Answer Answer: d. Explanation: None. How can the processor ignore other interrupts when it is servicing onea) By turning off the interrupt request lineb) By disabling the devices from sending the interruptsc) BY using edge- triggered request linesd) All of the above. View Answer Answer: d. Explanation: None. When dealing with multiple device interrupts , which mechanism is easy to implementa) Polling methodb) Vectored interruptsc) Interrupt nestingd) None of the above. View Answer Answer: a. Explanation: In this method the processor checks the IRQ bits of all the devices, which ever is enabled first that device is serviced. The interrupt servicing mechanism in which the reqesting device identifies itself to the processor to be serviced isa) Pollingb) Vectored interruptsc) Interrupt nestingd) Simultaneous requesting. View Answer Answer: b. Explanation: None. In vectored interrupts, how does the device indentify itself to the processor.?? By sending its device idb) By sending the machine code for the interrupt service routinec) By sending the starting address of the service routined) Either a or c. View Answer Answer: c. Explanation: By sending the starting address of the routine the device ids the routine required and thereby identifying itself. The code sent by the device in vectored interrupt is _____ longa) upto 1. View Answer Answer: d. Explanation: None. The starting address sent by the device in vectored interrupt is called asa) Location idb) Interrupt vectorc) Service locationd) Service id. View Answer Answer: b. Explanation: None. The processor indicates to the devices that it is ready to recieve interruptsa) By enabling the interrupt request lineb) By enabling the IRQ bitsc) By activating the interrupt acknowledge lined) Either a or b. View Answer Answer: c. Explanation: When the processor activates the acknowledge line the devices send their interrupts to the processor. We describe a protocol of input device communication below: i) Each device has a distinct address. The BUS controller scans each device in sequence of increasing address value to determine if the entity wishes to communicateiii) The device ready to communicate leaves its data in the I/O registeriv) The data is picked up and the controller moves to the step a. Identify the form of communication best describes the I/O mode amongst the following: a) Programmed mode of data transferb) DMAc) Interrupt moded) Polling. View Answer Answer: d. Explanation: In polling the processor checks each of the device if they wish to perform data transfer and if they do it performs the particular operation. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line…?? Neither vectored nor multiple interrupting devices is possible. Vectored interrupts is not possible but multiple interrupting devices is possible. Vectored interrupts is possible and multiple interrupting devices is not possible. Both vectored and multiple interrupting devices is possible. View Answer Answer: a. Explanation: None. Which table handle stores the addresses of the interrupt handling sub- routinesa) Interrupt- vector tableb) Vector tablec) Symbol link tabled) None of these. View Answer Answer: a. Explanation: None. Vectored- interruptingb) Daisy chainc) Priorityd) Polling. View Answer Answer: b. Explanation: In Daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority. In daisy chaining device 0 will pass the signal only if it has. Interrupt requestb) No interrupt requestc) Both a and bd) None of the above. View Answer Answer: b. Explanation: In daisy chaining since there is only one request line and only one acknowledge line, the acknowledge signal passes from device to device until the one with the interrupt is found. Parallel priority interruptb) Serial priority interruptc) Daisy chainingd) None of the above. View Answer Answer: a. Explanation: None. Massb) Markc) Maked) Mask. View Answer Answer: d. Explanation: None. The anded output of the bits of the interrupt register and the mask register are set as input of: a) Priority decoderb) Priority encoderc) Process id encoderd) Multiplexer. View Answer Answer: b. Explanation: In a parallel priority system, the priority of the device is obtained by anding the contents of the interrupt register and the mask register. ![]() How install Apache 2. PHP 5. 4 and My. SQL 5. Windows 7. Posted by newlife. Mar 1. 7, 2. 01. 2 in Windows | 2. Recently decided to install a working Apache 2. It is important that you practice as we go along. In this chapter, you will need to start afresh with two servers. You can use VirtualBox to create the CentOS servers.Apache Ant is an open-source tool for automating Java program build process. Similar to how the make utility builds an executable from source code and libraries using. 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Create a config directory under phpmyadmin. Open a browser and type localhost/phpmyadmin/setup/index. At this point you should have a working Apache / PHP / My. SQL installation running and ready for you to start developing !!! |
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